SR FlipFlop Using Case Statement Verilog Code

SR FlipFlop Using Case Statement Verilog Code
Verilog Code
module SR_FlipFlop(
    input J,
    input K,
     input clk,
    output Q,
    output Qbar
     );
reg Q,Qbar;

[email protected](posedge clk)
begin
    case({J,K})
    2’b0_0:Q<=Q;
    2’b0_1:Q<=1’b0;
    2’b1_0:Q<=1’b1;
    2’b1_1:Q<=1’bz;
endcase
end

endmodule

Test Bench 
module SRflipflopTB;

    // Inputs
    reg J;
    reg K;
    reg clk;

    // Outputs
    wire Q;
    wire Qbar;

    // Instantiate the Unit Under Test (UUT)
    SR_FlipFlop uut (
        .J(J),
        .K(K),
        .clk(clk),
        .Q(Q),
        .Qbar(Qbar)
    );
initial clk = 0;
    always #10 clk = ~clk;
    initial begin
        // Initialize Inputs
        J = 0;
        K = 0;
        clk = 0;

        // Wait 100 ns for global reset to finish
        #100;
       J=0;
        K=1;
       
        #100
        J=1;
        K=0;
       
      #100
        J=1;
        K=1;
       
        // Add stimulus here

    end
     
endmodule

Soon We will Provide Output Pics also

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