- Verilog

Verilog Code JK Flip Flop using Case Statement

Verilog Code :JK Flip Flop using Case Statement Verilog Code  module JKFlipFlop(    input J,    input K,     input clk,    output Q,    output Qbar        );reg Q,Qbar; always@(posedge clk)begin    case({J,K})    2’b0_0:Q<=Q;    2’b0_1:Q<=1’b0;    2’b1_0:Q<=1’b1;    2’b1_1:Q<=Qbar;endcaseendendmodule  Test Bench module JK_FlipFlop_TB;     // Inputs    reg J;    reg K;     // Outputs    wire Q;    wire Qbar;…

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