Verilog Code: Decoder (3:8) using if-else Verilog Code module Decoderusingifelse(data,out);input [2:0]data;output [7:0]out;reg [7:0]out;always@(data)begin if(data==7) out=1; else if(data==6) out=2; else if(data==5) out=4; else if(data==4) out=8; else if(data==3) out=16; else if(data==2) out=32; else if(data==1) out=64; else if(data==0) out=128; else out=0;endendmodule Test Bench module DecoderTB;…